1. Field of the Invention
The subject matter of the present invention pertains to a computer system, and more particularly, to an error detection mechanism in said computer system for detecting the existence of abnormal circuit conditions in a multitude of interface lines extending between circuit modules.
2. Description of the Prior Art
Circuit modules are connected together by a multitude of interface lines. Some of these lines are used as control lines for controlling the transfer of data from on module to another. Some of the control lines may be used during a data mode and a non-data mode whereas others of these control lines may be used only in the data mode. If an abnormal circuit condition occurred within one or more of these control lines, the one or more of these control lines would no longer perform their intended function.
An abnormal circuit condition is defined to be a failure of a receiver to sense the existence of an intended transmitted signal, and may be caused by an open-circuit or short circuit condition existing in one or more of the interface lines.
In order to detect the existence of abnormal circuit conditions within these control lines, redundant, duplex lines, corresponding to each of the control lines, were often utilized. For example, if a duplex line was associated with a control line, a signal transmitted from one module to another via said control line would also be transmitted via said duplex line. The control line and the duplex line were each attached to an input terminal of an exclusive OR gate. The presence of said signal at each input terminal of the exclusive OR gate would cause the generation of a zero output signal therefrom. Thus, the control line and the duplex line were each operational. However, if an abnormal circuit condition affected the operation of the control line, a signal would not be present at the input terminal of the exclusive OR gate corresponding to the control line. The exclusive OR gate would generate a high (binary one) output signal. The presence of a high output signal generated from the exclusive OR gate would indicate that an abnormal circuit condition affected either the control line or the duplex line. However, it is not cost effective nor is it necessarily feasible from an engineering standpoint to provide a redundant duplex line for each interface line extending from one circuit module to another circuit module.
The prior art, such as IBM Technical Disclosure Bulletin Vol. 12, No. 4, Sept. 1969, page 615, discloses one method of detecting the existence of an abnormal condition in a circuit. A signal is introduced as an input signal to the circuit and an output signal is developed. A compare circuit, such as an AND gate, compares the input signal with the output signal. An error signal is developed from the compare circuit if a correct output signal is not received by the compare cicuit corresponding to the input signal. However, this prior art fails to recognize the problems encountered when two or more circuit modules are connected together by a multitude of interface lines, namely, the possibility of the existence of abnormal circuit conditions in the multitude of interface lines and the impossibility of providing a redundant, duplex line for each interface line to detect the existence of an abnormal circuit condition in said interface line. The prior art also includes the following additional publications, each of which similarly fail to recognize said problems: IBM Technical Disclosure Bulletins, (1) Vol. 18, No. 3, Aug. 1975; page 928; (2) Vol. 11, No. 2, July 1968, page 197; (3 ) Vol. 24, No. 1 A, June 1981, page 24; (4) Vol. 21, No. 11, April 1979, page 4572; and (5) Vol. 7, No. 10, Mar. 1965, page 905.